1. Field of the Invention
The present invention relates in general to an integrated defect yield management and query system. More specifically, the defect/yield management system can collect the results of the defect and yield analyses for semiconductor wafers and dies that are generated by scribing the wafers during or after the semiconductor wafer fabrication process, and store these results in a query database. Thereafter, analyzers can analyze various defect events according to these stored test results, to learn the defect characteristics of various process devices. In addition, the system can also integrate with in-situ particle monitor to reflect the real-time process situation.
2. Description of Related Art
In the semiconductor wafer fabrication process, defects may occur in the fabricated wafers due to operational, mechanical or chemical control errors, or the environmental uncertainty. Defects on the wafers may affect the normal operation of integrated circuits, thereby reducing the fabrication yield. Especially, since the fabrication process of the integrated circuits is increasingly complicated and the dimensions of the integrated circuits are continuously shrinking, a particle having a diameter of only 0.3 .mu.m may cause a severe decrease in the production yield. Therefore, it is very difficult for analyzers to determine which process steps or devices may cause defects, to analyze the defect characteristics of the process devices in the production line, and to locate the defect positions on a wafer or a die.
FIG. 1 (Prior Art) schematically illustrates a defect analysis flowchart in a conventional semiconductor wafer fabrication process. As shown in FIG. 1, the defect analysis process may be roughly divided into two portions: an in-line process defect control portion (shown in the left part of FIG. 1) and an off-line defect analysis portion (shown in the right part of FIG. 1). In the in-line process defect control portion, semiconductor wafers are tested after particular process steps, such as a diffusion/thin film process 11, a photolithography process 12 or an etching process 13. During these processing steps, the semiconductor wafers may become defective in their bulk or on their surface due to uncertain process environments. Therefore, after these process steps, an inspection step after developer/etching/deposition (AD/EI) 20 is performed to examine the processed wafers by thoroughly inspecting a part of these semiconductor wafers or by scanning. Depending upon the particular defect condition noted during the inspection step 20, process parameters in the production line may be changed to reduce the likelihood of further defects occurring. Then, based on the inspection results, an image-capturing inspection 30 of the semiconductor wafers is performed to obtain an image showing the sharpness and the composition of defects by optical microscopes, Scanning Electron Microscope (SEM) and element dispersion spectrum. These test results acquired by the in-line inspection steps are immediately sent to a defect management system 10, which can classify and preserve these test results for subsequent analyses.
Once the entire semiconductor manufacturing process is complete, processed semiconductor wafers are analyzed off-line for defects. These off-line defect analyses include a wafer acceptance test/specification (WAT/SPC) 40, a quality control (QC) examination 50, a Circuit Probing/Final Test (CP/FT) yield test 60 and a reliability step 70. The WAT/SPC step 40 is used to examine the electrical characteristics of the wafers under test by suitable devices. The QC examination 50 is used to visually examine the appearance of the wafers undergoing testing, to decide whether the extant number of defects meets the customer requirements. Then, the CP/FT yield test 60 is used to estimate the process yield. At this time, the wafers are scribed into a plurality of dies and the final test is finished based on dies. Finally, the reliability test 70 is performed under various test conditions. Conventionally, although the QC examination 50, the CP/FT yield test 60 and the reliability test 70 all are used to analyze visible and invisible defects of the semiconductor wafers, the results acquired through these tests are sent to different departments of the production line to be analyzed. For example, the results acquired by the QC examination 50 and the reliability test 70 are passed to the quality control (QC) department, and the results of the reliability test 60 are sent to the product department. Thus, in a conventional defect analysis system, various defect-related data were distributed to different individual departments. Therefore, it is very difficult to deal with a specific defect event as a whole. In addition, historical defect records are also difficult to maintain.
Furthermore, the conventional process defect management system can not combine the in-situ monitoring equipment, such as particle monitors for controlling the particle number in the fabrication environment, with other in-line or off-line testing devices. In other words, the above-indicated in-situ control data can not be integrated with the in-line test data and the off-line test data. Therefore, it is difficult to provide a complete set of defect-related information for further and real-time analyses. In addition, personnel on the production line can not identify the defect causes in time, and, therefore, an improvement of the production yield is not apparent.
Furthermore, the defect-related information is distributed over the whole production line, and can not be acquired by a simpler interface for the analyzers and the personnel on the production line. This reduces the efficiency of the defect analyses.